Fabricating semiconductor devices such as logic and memory devices typically includes processing a substrate, such as a semiconductor wafer, using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing (CMP), etching, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a single semiconductor wafer and then separated into individual semiconductor devices.
As used throughout the present disclosure, the term “wafer” generally refers to substrates formed of a semiconductor or non-semiconductor material. For example, a semiconductor or non-semiconductor material may include, but is not limited to, monocrystalline silicon, gallium arsenide, and indium phosphide. A wafer may include one or more layers. For example, such layers may include, but are not limited to, a resist, a dielectric material, a conductive material, and a semiconductive material. Many different types of such layers are known in the art, and the term wafer as used herein is intended to encompass a wafer on which all types of such layers may be formed. One or more layers formed on a wafer may be patterned or unpatterned. For example, a wafer may include a plurality of dies, each having repeatable patterned features. Formation and processing of such layers of material may ultimately result in completed devices. Many different types of devices may be formed on a wafer, and the term wafer as used herein is intended to encompass a wafer on which any type of device known in the art is being fabricated.
Electron-beam lithography, in many instances, is used to print/pattern individual device patterns or features. These patterns or features are often combined with additional device patterns or features to create a patterned semiconductor device. In addition, extreme ultraviolet (EUV) light lithography is also commonly used to print individual patterns or features of a semiconductor device.
Currently available patterning tool alignment methods are generally limited. For example, e-beam alignment typically is carried out one beam at a time, with the process being repeated over entire patterns or targets. The measurement of accuracy or inaccuracy of patterns or targets created by a single beam of a multi-beam patterning tool is time-intensive. Additionally, irregularities or inaccuracies in patterning with unaligned multi-beam systems are often cumulative because different beams may be used to print the various features of each pattern. Single-beam systems tend to increase the time of patterning, while multi-beam systems increase inaccuracy, resulting in increases in cost. Therefore, it is desirable to provide a method and system that cures the deficiencies of the prior art.